This invention relates to a semiconductor memory device and to the manufacturing method of the semiconductor memory device. In particular, this invention relates to a peripheral structure of the cell-capacitor of DRAM and to the method of fabricating the peripheral structure of the cell-capacitor.
Generally speaking, semiconductor memory devices are still demanded to be further improved in various aspects such as the progress of refinement, the reducing the power supply voltage, the higher operating speed, higher reliability, etc. In particular, the refinement technique for DRAM (Dynamic Random Access Memory) is now increasingly promoted so that the area to be occupied by the memory cell unit is increasingly miniaturized. Therefore, the issue to be solved urgently at present is how to secure a sufficient capacity of cell-capacitor within a limited area of cell.
The capacity of cell-capacitor can be enlarged by increasing the surface area of the cell-capacitor. Under the circumstances, a lot of proposals have been set forth so far for realizing both of the enlargement of surface area of cell-capacitor and the refinement of cell-capacitor.
One example of the conventional structure wherein the surface area of cell-capacitor can be increased may be represented by a cylinder structure which is set forth in a publication: W. Wakamiya et al., "Novel Stacked Capacitor Cell for 64 Mb DRAM", Symposium on VLSI Technology Digest, pp. 69-70, 1989. This structure is one kind of stacked capacitor wherein a cylindrical capacitor is three-dimensionally disposed so as to increase the surface area, while suppressing the area occupied by the capacitor. However, this cylinder structure is defective in that it is difficult to perform the global flattening of interlayer insulating film covering the cell-capacitor. In view of overcoming this problem, Japanese Patent Laid Open No. 11-26718 sets forth a process which is capable of simplifying this flattening step even in the stacked capacitor of cylinder structure. However, if it is tried to secure the flatness of an interlayer insulating film covering the stacked capacitor, the number of manufacturing steps is inevitably increased, resulting in an increase in manufacturing cost. Meantime, a problem involved in the manufacture of DRAM is an especially severe competition among manufacturers in terms of manufacturing cost, so that various ideas have been adopted by each manufacturer at present for the purpose of simplifying as much as possible the fabricating process of DRAM. Therefore, as far as DRAM is concerned, it may not be appropriate in view of the present situations as mentioned above to adopt a manufacturing method which necessitates an increase in number of manufacturing steps.
Additionally, the manufacturing method set forth in Japanese Patent Laid Open No. 11-26718 is defective in that the properties of the cell-capacitor of DRAM may be deteriorated. The reasons for this will be explained below with reference to FIG. 1. FIG. 1 is a cross-sectional view illustrating the memory cell array region, the marginal portion of memory cell array region and peripheral circuit region of a conventional DRAM. By the way, this memory cell array region represents a region where a memory cell consisting of a cell transistor and a cell-capacitor are to be formed. This peripheral circuit region represents a region where various kinds of peripheral circuits (excluding the memory cell) such as a sense amplifier and a decoder are to be formed. This marginal portion of memory cell array region represents a region which constitutes a boundary between the memory cell array region and the peripheral circuit region.
As shown in FIG. 1, a silicon substrate 10 is provided with element regions AA (Active Area) and element isolation regions STI (Shallow Trench Isolation) surrounding the element regions AA. A cell transistor (not shown) is formed in each of the element regions AA within the memory cell array region, and a peripheral transistor is formed in each of the element regions AA within the peripheral circuit region. The peripheral transistor is constituted by a gate insulating film 11 formed on the silicon substrate 10, a gate electrode 12 formed on the gate insulating film 11, and impurity diffusion layers 13 formed inside the substrate 10 and functioning as a source region or a drain region. The gate electrode 12 is covered by an SiN film 14 for instance. The structure of the cell transistor is fundamentally the same as that of this peripheral transistor, wherein the gate electrode of the cell transistor functions as a word line 15.
Further, an interlayer insulating film 16 is deposited on the silicon substrate 10 so as to cover the cell transistor and the peripheral transistor. The interlayer insulating film 16 is provided therein with bit lines 17 located within the memory cell array region and connected with the drain region of the cell transistor. A metallic wiring layer 18 which is connected with the impurity diffusion layer 13 of the peripheral transistor is formed within the peripheral circuit region and at the same level as that the bit lines 17. Additionally, contact plugs 19 connected with the source region of the cell transistor are formed within the memory cell array region. This contact plugs 19 are formed for the purpose of connecting the cell transistor with the cell-capacitor.
Next, the structure disposed above the interlayer insulating film 16 covering these transistors, the bit lines 17 and the metallic wiring layer 18 will be explained.
An SiN film 20 is deposited on the interlayer insulating film 16 except the portions where the top surface of the contact plugs 19 is exposed. Further, as far as the marginal portion of memory cell array region and the peripheral circuit region are concerned, an SiO.sub.2 film 21 is deposited on the SiN film 20. On the other hand, as far as the memory cell array region is concerned, a storage node electrode 22 of cylinder type is disposed enabling it to be contacted with the contact plug 19 at the bottom portion thereof. Further, as far as the region where the memory cell array region is contacted with the marginal portion of memory cell array region is concerned, the storage node electrode 22 is formed along the sidewall of the SiO.sub.2 film 21. This storage node electrode 22 is formed also on a portion of the SiO.sub.2 film 21 which is located within the marginal portion of memory cell array region. Furthermore, as far as the memory cell array region and the marginal portion of memory cell array region are concerned, a capacitor insulating film 23 and a plate electrode 24 are deposited over these regions to thereby constitute a cell-capacitor.
Additionally, an interlayer insulating film 25 is deposited over the memory cell array region, the marginal portion of memory cell array region and the peripheral circuit region. As far as the marginal portion of memory cell array region is concerned, a contact plug 26 connected with the plate electrode 24 is formed in the interlayer insulating film 25, and as far as the peripheral circuit region is concerned, a contact plug 27 is formed connecting with the metallic wiring layer 18 being at the same level as that of the bit line. Further, metallic wiring layers 28 and 29 are formed so as to be connected with these contact plugs 26 and 27, respectively, thereby accomplishing the DRAM.
According to this structure of the DRAM, while a cell-capacitor of cylinder type is formed on the interlayer insulating film 16 as far as the memory cell array region is concerned, the SiO.sub.2 film 21 is formed up to almost the same level as the top surface of the storage node electrode 22 of the cell-capacitor in both of the marginal portion of memory cell array region and the peripheral circuit region. As a result, it becomes possible to assure the flatness of the interlayer insulating film 25 covering the storage node electrode 22 and the SiO.sub.2 film 21.
The contact plug 26 which is indispensable for the purpose of giving an electric potential to the plate electrode is generally disposed at the marginal portion of memory cell array region. Further, for the purpose of simplifying the fabricating process, a contact hole 30 for forming the contact plug 26 is generally formed concurrently with a contact hole 31 for forming the contact plug 27 of the peripheral circuit region by the RIE (Reactive Ion Etching) method for instance.
However, while the bottom of the contact hole 30 of the memory cell array region is disposed at the same level with the top surface of the plate electrode 24 which is disposed over the SiO.sub.2 film 21, the bottom of the contact hole 31 of the peripheral circuit region is disposed at the same level with the top surface of the bit line 17. Therefore, if these two contact holes 30 and 31 are concurrently formed, despite that the formation of the contact hole 30 has been accomplished beforehand, the bottom of contact hole 30 is still subjected to a plasma damage due to RIE until the formation of the contact hole 31 is accomplished. As a result, the properties of the cell-capacitor may be deteriorated.
Moreover, the storage node electrode 22, capacitor insulating film 23 and plate electrode 24 of the cell-capacitor that will be disposed at a memory cell array region contacting with the marginal portion of memory cell array region must be formed along the sidewall and top surface of the SiO.sub.2 film 21. If the electrode 22, film 23, and electrode 24 are so formed, the resultant cell-capacitor differs in structure from that of the cell-capacitors located at other regions. The capacitor inevitably become a dummy capacitor. This deteriorates the areal efficiency of the DRAM.